Execution and Verification of UML State Machines with Erlang
作者： Ricardo J. Rodríguez , Lars-Åke Fredlund , Ángel Herranz , Julio Mariño
DOI: 10.1007/978-3-319-10431-7_22
关键词:
摘要: Validation of a system design enables to discover specification errors before it is implemented (or tested), thus hopefully reducing the development cost and time. The Unified Modelling Language (UML) becoming widely accepted for early analysis requirements safety-critical systems, although better balance between UML’s undisputed flexibility, precise unambiguous semantics, needed. In this paper we introduce UMerL, tool that capable executing formally verifying UML diagrams (namely, state machine, class object diagrams) by means translation its behavioural information into Erlang. use illustrated with an example in embedded software design.
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