Hybrid Digit-Serial Multiplier for Shifted Polynomial Basis of GF(2 m )

摘要: Recently, a shifted polynomial basis is variation of representation. Such kind provides better performance in designing bit-parallel and subquadratic space complexity multipliers over binary extension fields. In this paper, we study new multiplication algorithm to implement hybrid digit-serial multiplier. The proposed effectively integrates classic schoolbook multiplication, Karatsuba algorithms reduce computational complexity, the modular with reduction. We note that, comparably, architecture achieves lower computation time higher bit-throughput compared best known multipliers. Our can be modular, regular, suitable for very-large-scale integration (VLSI) implementations. makes hardware implementations cryptographic systems more high-performance, are thus much efficient applications such as elliptic curve cryptography (ECC) pairing computation.