Digital cancellation of D/A converter noise in pipelined A/D converters

摘要: Pipelined analog-to-digital converters (ADCs) tend to be sensitive component mismatches in their internal digital-to-analog (DACs), The give rise error, referred as DAC noise, which is not attenuated or cancelled along the pipeline are other types of noise. This paper describes an all-digital technique that significantly mitigates this problem. continuously measures and cancels portion ADC error arising from noise during normal operation ADC, so no special calibration signal auto-calibration phase required. details described context a nominal 14-bit pipelined example at both processing register transfer levels. Through example, demonstrates presence realistic matching limitations can improve overall accuracy by several bits with only moderate digital hardware complexity.