Square law analog-to-digital converter

摘要: A plural stage analog-to-digital converter with a square law transfer characteristic is described. The comprises in typical embodiment three identical stages the first having fixed reference voltage applied thereto. More or less can be used as desired. pair of resistive ladder networks resistors thereof arranged quadratic fashion employed each converter. divide to into plurality voltages predetermined magnitude. comparators compare divided respective an unknown analog input signal which also stage. for second are obtained from and third decoder coupled deriving output representative level