A test methodology for interconnect structures of LUT-based FPGAs

作者： H. Michinishi , T. Yokohira , T. Okamoto , T. Inoue , H. Fujiwara

DOI: 10.1109/ATS.1996.555139

关键词:

摘要: In this paper we consider testing for programmable interconnect structures of look-up table based FPGAs. The structure considered in the consists interconnecting wires and points (switches) to join them. As fault models, stuck-at faults wires, extra-device missing-device are considered. We heuristically derive test procedures then show their validness complexity.

参考文章(3)

Field-Programmable Gate Array Technology Kluwer Academic Publishers. ,(1994) , 10.1007/978-1-4615-2742-8

T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira, T. Okamoto, Universal test complexity of field-programmable gate arrays asian test symposium. pp. 119- ,(1995) , 10.1109/ATS.1995.485345

I. Pomeranz, S.M. Reddy, Testability considerations in technology mapping Proceedings of IEEE 3rd Asian Test Symposium (ATS). pp. 79- ,(1994) , 10.1109/ATS.1994.367238

A test methodology for interconnect structures of LUT-based FPGAs

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A test methodology for interconnect structures of LUT-based FPGAs

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