A 54 Mbps (3,6)-regular FPGA LDPC decoder
作者： Tong Zhang , K.K. Parhi
DOI: 10.1109/SIPS.2002.1049697
关键词:
摘要: Applying a joint code and decoder design methodology, we develop high-speed (3, k)-regular LDPC partly parallel architecture, based on which 9216-bit, rate-1/2 (3,6)-regular is implemented an Xilinx FPGA device. When performing maximum 18 iterations for each block decoding, this supports symbol throughput of 54 Mbps achieves BER 10/sup -6/ at 2 dB over AWGN channel.
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