Identifying DC bias conditions for maximum DC current in digitally-assisted analog design

摘要: We propose a novel methodology for maximizing DC current in digitally-assisted analog circuit. The proposed identifies set of bias voltages and digital mode selection signals that maximizes the through either particular wire segment or power/ground bus. This technique enables sensitization EM related faults. First, channel-connected graph is built from mixed signal transistor circuit, then activation condition formulated as satisfiability constraints annotated graph. results weighted constraint satisfaction(WCS) formulation. To best author's knowledge, this problem has not been previously studied.