作者: Kaizo Yamamoto , 海三 山本 , 禎彦 杉浦 , Sadahiko Sugiura
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摘要: PURPOSE:To prevent an operation state from being deviated design due to the drop of drain instantaneous voltage FET be amplification element in F class power amplifier a level less than knee voltage. CONSTITUTION:A serial circuit consisting diode 8 and capacitor 7 is connected loads 4 6 for 1 parallel bias (VD-VK) applied 8. When absolute value output exceeds (VD-VK), turned on, AC ground set up peak limited (VD-VK). Thereby limited, so that reduction current suppressed, distortion removed ideal can attained.