Processor powerdown operation using intermittent bursts of instruction clock

作者: Richard Joseph Niescier , Laurence E. Bays , Jalil Fadavi-Ardekani , Kenneth Daniel Fitch

DOI:

关键词:

摘要: An instruction clock of a processing unit in low power mode accordance with the principles present invention is qualified burst control signal. The signal allowed to start and stop flow relevant unit. In disclosed embodiment, master by circuit provide bursts an To operate cycle unit, user pre-programs length, into register set length cycles A maximum counter value sets period provided As long as current less than or equal pre-programmed allows controller pass other thus savings adjustable according combined values value.

参考文章(10)
Yoshitomo Kuwamoto, Hidefumi Kimura, Masanori Ienaka, Hideaki Watanabe, Jun'ichi Nakagawa, Power saving intermittently operated phase locked loop ,(1986)
Nikhil A. Mehta, Larry Leonard Lamano, Richard Alan Vrba, James Stevens Klecka, Kyran Wilfred Fey, High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors ,(1996)
Stephen D. Weitzel, Renitia J. Bertoluzzi, Robert T. Jackson, Integrated dynamic power dissipation control system for very large scale integrated (VLSI) chips ,(1995)
Peter J. Puskas, David Arata, Frequency modulated ultrasonic generator ,(1997)
Frederic C. Amerson, Vinod K. Kathail, Michael S. Schlansker, Rajiv Gupta, Memory processor that prevents errors when load instructions are moved in the execution sequence ,(1994)