System and method for ESD protection

摘要: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS circuit is described. A front end provides programmable attenuation gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters onto the substrate in conjunction reject mixers to provide sufficient frequency rejection. Filter tuning inductor Q compensation over temperature are performed chip. The utilize multi track spiral inductors. tuned using local oscillators tune substitute filter, scaling during filter component values those of being tuned. In filtering, planning additional advantageous choice oscillator signal generation methods chip by PLL out band oscillation direct synthesis for oscillator. VCOs PLLs centered control center capacitance range. differential crystal used as reference. Differential transmission throughout receiver. ESD protection provided pad ring clamping structure that maintains integrity. Also shunts at each pin discharge build up. gate boosting small RF performance, minimal parasitic loading.