A system to detect timing problems in digital circuits

Satoshi Ohtake, Hideo Fujiwara, Hiroshi Iwata, An Approach to RTL False Path Mapping Using Uniqueness of Paths 奈良先端科学技術大学院大学. ,(2009)

J. J. Horning, W. M. Waite, J. Eickel, W. M. McKeeman, P. C. Poole, U. Hill, M. Griffiths, F. L. Bauer, C. H. A. Koster, F. L. De Remer, J. Hartmanis, G. Goos, Compiler Construction: An Advanced Course ,(1974)

Yuji Kukimoto, Robert K. Brayton, Timing-safe false path removal for combinational modules international conference on computer aided design. pp. 544- 550 ,(1999) , 10.5555/339492.340075

S. Perremans, L. Claesen, H. De Man, Static Timing Analysis of Dynamically Sensitizable Paths design automation conference. pp. 568- 573 ,(1989) , 10.1145/74382.74477

Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe, Waiting false path analysis of sequential logic circuits for performance optimization international conference on computer aided design. pp. 392- 395 ,(1998) , 10.1145/288548.289059

D. H. Du, S. H. Yen, S. Ghanta, On the General False Path Problem in Timing Analysis design automation conference. pp. 555- 560 ,(1989) , 10.1145/74382.74475

Jason Govig, Mike Hutton, Martin D. F. Wong, Deming Chen, Lei Cheng, Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains international conference on computer aided design. pp. 370- 375 ,(2007) , 10.5555/1326073.1326149

M. Nourani, C.A. Papachristou, False path exclusion in delay analysis of RTL structures IEEE Transactions on Very Large Scale Integration Systems. ,vol. 10, pp. 30- 43 ,(2002) , 10.1109/92.988728