High-Performance Embedded Architecture and Compilation Roadmap

摘要: One of the key deliverables EU HiPEAC FP6 Network Excellence is a roadmap on high-performance embedded architecture and compilation --- Roadmap for short. This paper result roadmapping process that took place within community beyond. It concisely describes research challenges ahead us it will be used to steer efforts. The details several need tackled in coming decade, order achieve scalable performance multi-core systems, make them practical mainstream technology systems. The organized around 10 central themes: (i) single core architecture, (ii) (iii) interconnection networks, (iv) programming models tools, (v) compilation, (vi) run-time (vii) benchmarking, (viii) simulation system modeling, (ix) reconfigurable computing, (x) real-time systems. Per theme, list identified. In total 55 are listed this roadmap. The can serve as valuable source reference researchers active field, help companies building their own R&D roadmap, although not intended tutorial document even an introduction scientists professionals interested learning about compilation.