Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon Era

作者: Mohaddeseh Hoveida , Fatemeh Aghaaliakbari , Ramin Bashizade , Mohammad Arjomand , Hamid Sarbazi-Azad

DOI: 10.1145/3055202

关键词:

摘要: The failure of Dennard scaling has led to the utilization wall that is source dark silicon and limits percentage a chip can actively switch within given power budget. To address this issue, structure needed guarantee limited budget along with providing sufficient flexibility performance for different applications various communication requirements. In article, we present general-purpose platform future many-core Chip-Multiprocessors (CMPs) benefits from advantages clustering, Network-on-Chip (NoC) resource sharing among cores, gating unused components clusters. We also propose two task mapping methods proposed in which active cores are dispersed appropriately, so an excess be obtained. Our evaluations reveal first second mechanisms respectively reduce execution time by up 28.6% 39.2% NoC consumption 11.1% 10%, gain 7.6% 13.4% over baseline architecture.

参考文章(42)
Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu, A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints ACM Transactions on Architecture and Code Optimization. ,vol. 7, pp. 1- 30 ,(2010) , 10.1145/1736065.1736066
Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Awet Yemane Weldezion, Pasi Liljeberg, Juha Plosila, Axel Jantsch, Hannu Tenhunen, Dark silicon aware power management for manycore systems under dynamic workloads international conference on computer design. pp. 509- 512 ,(2014) , 10.1109/ICCD.2014.6974729
Marcelo Mandelli, Alexandre Amory, Luciano Ost, Fernando Gehm Moraes, Multi-task dynamic mapping onto NoC-based MPSoCs Proceedings of the 24th symposium on Integrated circuits and systems design - SBCCI '11. pp. 191- 196 ,(2011) , 10.1145/2020876.2020920
W.J. Dally, Virtual-channel flow control IEEE Transactions on Parallel and Distributed Systems. ,vol. 3, pp. 194- 205 ,(1992) , 10.1109/71.127260
S. Vangal, N. Borkar, A. Singh, S. Borkar, Y. Hoskote, A 5-GHz Mesh Interconnect for a Teraflops Processor IEEE Micro. ,vol. 27, pp. 51- 61 ,(2007) , 10.1109/MM.2007.77
Ganesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson, QsCores Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11. pp. 163- 174 ,(2011) , 10.1145/2155620.2155640
Nan Jiang, Daniel U Becker, George Michelogiannakis, James Balfour, Brian Towles, David E Shaw, John Kim, William J Dally, A detailed and flexible cycle-accurate Network-on-Chip simulator international symposium on performance analysis of systems and software. pp. 86- 96 ,(2013) , 10.1109/ISPASS.2013.6557149
Jia Zhan, Yuan Xie, Guangyu Sun, NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era design automation conference. pp. 1- 6 ,(2014) , 10.1145/2593069.2593165
Chen-Ling Chou, Radu Marculescu, Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis - CODES+ISSS '07. pp. 161- 166 ,(2007) , 10.1145/1289816.1289857
Chen-Ling Chou, U.Y. Ogras, R. Marculescu, Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 27, pp. 1866- 1879 ,(2008) , 10.1109/TCAD.2008.2003301