Methods for layout verification for polysilicon cell edge structures in FinFET standard cells

摘要: Methods for standard cells using finFET cell structures with polysilicon on OD edges. Standard are defined transistors and having gate forming a transistor at an intersection semiconductor fin. Polysilicon dummy formed the edges of active areas or cells. In design flow, pre-layout netlist schematic includes three terminal MOS device corresponding to structure cell. After automated place route process forms layout cells, post is extracted. Where two abut one another, single common boundary. A versus comparison then performed comparing post-layout verify obtained. Additional methods disclosed.