作者: Hironao Takahashi
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摘要: A data transmission device includes a memory cache table ( 4 ) composed of DRAM memory, standard 2.5″ hard disk 5 ), control CPU 7 FPGA 6 (or ASIC), interface 3 and backup battery. The is unitized in the same external shape as 3.5″ connected to computer 2 via ASIC) manages based on actions by ).