Placement techniques for the physical synthesis of nanometer-scale integrated circuits

摘要: Placement is a critical component in the physical synthesis of nanometer-scale integrated circuits. circuit modules determines to large extent interconnect length and routing resource demand. Interconnect has direct impact on delay, which become determining factor performance process technology. In addition, power. Hence, quality placement significantly affects ability tool or designer achieve design closure. this work, efficient high techniques have been developed for multi-million gate circuits nanometer regime. The focus these are: (a) global legalization mixed-size minimize length, power demand, (b) incremental via timing optimization effectiveness demonstrated by: comparing them with existing approaches that perform placement, embedding within stateof-the-art industrial used 65nm 45nm technology nodes.