System and method for providing dynamic clock and voltage scaling (dcvs) aware interprocessor communication

作者: Shirish Kumar Agarwal , Sravan Kumar Ambapuram , Krishna Vsssr Vanka

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摘要: Systems and methods that allow for Dynamic Clock Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received first processing component. Additionally, component also receives workload information about second operating under dynamic clock voltage scaling (DCVS). A determination made, based part on information, whether to send from buffer, providing cost effective ability reduce power consumption improved battery life PCDs multi-cores multi-CPUs implementing DCVS algorithms logic.

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