Globally asynchronous communication architecture for system on chip
作者： Edith Beigne , Pascal Vivet , Fabien Clermidy
DOI:
关键词:
摘要: This invention relates to the domain of Networks on Chips (NoC) and a method transferring data in network chip, particularly using an asynchronous “send/accept” type protocol. The also chip used implement this method.
lens.org 参考文章(17)
Jean-Baptiste Rigaud, Spécification de bibliothèques pour la synthèse de circuits asynchrones Institut National Polytechnique de Grenoble - INPG. ,(2002)
J-B. Rigaud, J. Quartana, L. Fesquet, M. Renaudin, Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies. pp. 313- 324 ,(2001) , 10.1007/978-0-387-35597-9_27
M. Renaudin, P. Vivet, F. Robin, ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor international symposium on advanced research in asynchronous circuits and systems. pp. 0022- ,(1998) , 10.1109/ASYNC.1998.666491
T. Felicijan, S.B. Furber, An asynchronous on-chip network router with quality-of-service (QoS) support symposium on cloud computing. pp. 274- 277 ,(2004) , 10.1109/SOCC.2004.1362432
John Hesse, Coke Reed, David Murphy, Means and apparatus for a scaleable congestion free switching system with intelligent control III ,(2008)
Uri Cummings, Andrew Lines, Asynchronous crossbar with deterministic or arbitrated control ,(2002)
Alain J. Martin, Synthesis of Asynchronous VLSI Circuits California Institute of Technology. ,(1991)
Howard Thomas Olnowich, Arthur Robert Williams, Michael Hans Fisher, Jehoshua Bruck, John David Jabusch, Joel Mark Gould, Method of simultaneously attempting parallel path connections in a multi-stage interconnection network ,(1998)
J. Bainbridge, S. Furber, Chain: a delay-insensitive chip area interconnect IEEE Micro. ,vol. 22, pp. 16- 23 ,(2002) , 10.1109/MM.2002.1044296
P. Wielage, K. G. W. Goossens, E. Rijpkema, E. Waterlander, A. Radulescu, J. van Meerbergen, J. Dielissen, Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip design, automation, and test in europe. ,vol. 150, pp. 10350- 10355 ,(2003) , 10.5555/789083.1022751