Vertical bipolar read access for low voltage memory cell
作者： Leonard Forbes
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摘要: A memory device is described which has an n-channel FET access transistor coupled between a cell and data communication line. An NPN bipolar also the line in parallel to transistor. base connection of as body control threshold voltage variations During operation used for writing cell, while read operations conjunction with current sense amplifier circuit. The transistors are fabricated single vertical pillar.
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