Dual link DVI transmitter serviced by single Phase Locked Loop
作者： Stephen G. Petilli , Richard Berard , Christopher R. Pasqualino , Jeffrey Bauch
DOI:
关键词:
摘要: A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) service both primary and secondary during mode operations. The structure of includes PLL PLL. produces clock clock. During operations, is used while link. However,
google.co.uk 参考文章(18)
Robert R. Cordell, Digital phase aligner with outrigger sampling ,(1987)
Adam Opoczynski, Jeffrey Brede, James W. Ott, Phase locked loop using a counter and a microcontroller to produce VCXO control signals ,(1994)
Po Ngan Zee, Christopher R. Pasqualino, Synchronization of data links in a multiple link receiver ,(2002)
Scott W. Lowrey, Jeffrey A. Porter, Broadband digital phase aligner ,(1992)
Senani Gunaratna, SunilKumar G. Mudunuri, James M. Apland, Ket-Chong Yap, Andrew K. Chan, Serializer/deserializer embedded in a programmable device ,(2001)
Francois Ducaroir, Karl S. Nakamura, Michael O. Jenkins, Using multiple high speed serial lines to transmit high data rates while compensating for overall skew ,(1997)
Donald Wilkins, Samuel Green, System and method for transmitting digital video over an optical fiber ,(2002)
Deog-Kyoon Jeong, Kyeongho Lee, System and method for high-speed skew-insensitive multi-channel data transmission ,(1997)
Regis Gratacap, Robert Robinett, Bandwidth optimization of video program bearing transport streams ,(2001)
Min-Kyu Kim, Gyudong Kim, Methods and systems for sending side-channel data during data inactive period ,(2002)