作者: Neeraj K. Chasta
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摘要: This paper, presents an idea for analog current comparison which compares input signal and reference currents with high speed accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations are amplified a compared output is developed. Cascaded inverter stages used to generate final CMOS compatible voltage. Power consumption can be controlled by the applied bias The comparator designed studied at 180nm process technology supply 3V. Keywords-Current Mode, Comparator, High Speed, Resolution.