An Energy and Performance Exploration of Network-on-Chip Architectures

摘要: In this paper, we explore the designs of a circuit-switched router, wormhole quality-of-service (QoS) supporting virtual channel router and speculative accurately evaluate energy-performance tradeoffs they offer. Power results from placed routed in 90-nm CMOS process show that all architectures dissipate significant idle state power. The additional energy required to route packet through is then shown be dominated by data path. This leads key result that, if trend continues, use more elaborate control can justified will not immediately limited budget. A performance analysis also shows dynamic resource allocation lowest network latencies, while static may used meet QoS goals. Combining power figures allows an energy-latency product calculated judge efficiency each networks. was have very similar providing better performance, its for general purpose designs. Finally, area metrics are presented allow comparison implementation costs.