Low-Latency High-Throughput Systolic Multipliers Over $GF(2^{m})$ for NIST Recommended Pentanomials

摘要: Recently, finite field multipliers having high-throughput rate and low-latency have gained great attention in emerging cryptographic systems, but such over GF(2 m ) for National Institute Standard Technology (NIST) pentanomials are not so abundant. In this paper, we present two pairs of bit-parallel digit-serial systolic based on NIST pentanomials. We propose a novel decomposition technique to realize the multiplication by several parallel arrays 2-dimensional (2-D) structure (BP-I) with critical-path 2TX, where TX is propagation delay an XOR gate. The 2-D then projected along vertical direction obtain (DS-I) same critical-path. For applications, another pair (BP-II) (DS-II) structures modular reduction technique, reduced (TA+TX), TA being AND A strategy data sharing between processing elements (PEs) adjacent has been proposed reduce area-complexity BP-I BP-II further. From synthesis results, it shown that significantly lower latency higher throughput than existing designs. To best authors' knowledge, first report fields independent field-order.