作者: Bidyut Parruck , Daniel C. Upp
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摘要: An apparatus and method for transferring a data payload (SPE) from first substantially SONET signal into second of different frequency. A circuit (43a) extracting the SPE bytes sending bytes, according to clock, FIFO (60) storage; (47a) obtaining building signal; (70) comparing relative byte phases clocks. To avoid read/write conflicts in FIFO, comparison generates sends (34a) which causes change phase at are sent FIFO. adjust frequency differences between signals, builds when two signals have slipped each other.