Device and Circuit Performance of the Future Hybrid III–V and Ge-Based CMOS Technology

摘要: The device and circuit performance of a 20-nm gate length InGaAs Ge hybrid CMOS based on an implant free quantum well (QW) architecture is studied using multiscale approach combining ensemble Monte Carlo simulation, drift-diffusion compact modeling, TCAD mixed-mode simulation. We have found that the QW doped substrate, used in CMOS, help to reduce short-channel effects by enhancing carrier confinement. also reduces destructive impact low density states III–V materials. In addition, calculated access resistance be much lower than Si counterparts thanks heavily overgrowth source/drain contact. predict overall capacitance large drive current when compared with Si-CMOS leads significant reduction propagation time delay ( ${\sim }5.5$ ps).