Multimode, uniform-latency clock generation circuit
作者： William James Goodall , Fadi Adel Hamdan , Jeffrey Herbert Fischer
DOI:
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摘要: A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the CGC generates a pulse signal via path responsive to chopping being active and phase same inactive. The activated mode control input in first state deactivated either second or plurality of enable signals more embodiments, included microprocessor for providing inter-stage pulsed sequential storage elements when operating timing sensitive insensitive mode.
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