Error correcting code protected quasi-static bit communication on a high-speed bus
作者： Robert J. Reese , Kevin C. Gower , Martin L. Schmatz , Peter Buchmann , Michael R. Trombley
DOI:
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摘要: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit (SBC) on a high-speed bus are provided. The device includes sampling logic to capture data from the using clock SBC samples an clock. is slower than also finite state machine (FSM) detect received command in response static pattern persisting predetermined number of decoding decode command.
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