Shift-shuffle memory system with rapid sequential access

摘要: A shift register memory having interconnections among its internal stages permitting stored data to be rearranged in two different ways. first set of permits the usual cyclic rotation response a ''''shift'''' control pulse. second shuffle pattern ''''shuffle'''' pulse, similar rearrangement cards deck when shuffled. pair registers records current state arrangement. Addressing circuitry calculates present storage location an addressed datum from this information. Additional generates accessing sequence and pulses which brings output stage register. After at succeeding addresses have been accessed fashion, all reordered may with single pulse per address.