Integrated logic circuit including impedance fault detection

摘要: An integrated logic circuit according to the present invention includes a plurality of elements, such as field effect transistors, for performing combinational function, and at least one test controlled-impedance element loading causing first digital output signal be produced when impedance under is within predetermined range produce another outside range. The elements typically comprise transistors are sized in accordance with series constraints. constraints obtained by considering operation various fault conditions (high, low intermediate) deriving size relationships between values elements. faults capable being detected include conventional stuck-on (LIF) arid stuck-off (HIF) also intermediate (IHIF, ILIF) caused too high or an transistor's on- off-state modes operation, respectively.