作者: Gheorghe Serban , Laurentiu Ionescu , Alin Mazare , Vlad Barbu
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摘要: In this paper we present an evolvable hardware structure based on a Boolean functions network implemented with the basic multiplexer circuit and configured by genetic algorithm. Even if is large research area (beginning in 1996) main problem which remains integration one single chip of entire system consists reconfigurable algorithm: build intrinsic hardware. Another how to increase convergence speed as can be used real time applications. our possible solution these problems. One (Xilinx Spartan 3) performed using algorithm internal block RAM memories, shift registers circuits. To parallel sorting/testing blocks are has pipeline architecture allow execution same genetics operators, testing fitness computation.