Statistics Inspired Hardware Architectures For Image And Video Processing

摘要: Conventional digital arithmetic circuits are designed to operate on a specified range of operand magnitudes.The architecture these is typically developed improve the area time characteristics and obtain an energy efficient implementation operating at desired throughput.Moreover, required provide full precision for dynamic operands speed worst case.Albeit correctness results ensured, input data statistics not taken into account. Resultantly, redundant computations performed since information content sequence in certain applications, such as image video processing, known be much less than simple binary descriptions used by conventional circuits. However, run identification exploitation latent redundancy non trivial owing diverse statistical nature data. Although efforts have been made past design low power architectures exploiting patterns magnitudes operands, few attempts logic processing efficiency harnessing properties inputs.It seems conducive application specific hardware that explicitly incorporates while computing consequently saves precious computation cycles or resources which otherwise wasted computations. This thesis proposes approaches utilize inherent applications achieve most economical tradeoffs between resources, precision.Specifically, modifications enhancements approaches, namely Distributed Arithmetic, Sub-Expression Sharing, Fast FIR parallel filtering Approximate Processing reported further enhance their efficiency.Conventional Arithmetic approach trade-off with has modified include Memoization based Look Up Tables storage partial from computations.This modification harnesses bit level redundancies leads decrease average requiring proportionately lesser increase resource requirements.The proposed implement Color Space Conversion module incorporation Instruction Set Architecture enhancement open-source Intellectual Property Core OR1200 32-bit processor. Similarly, Sharing techniques complexity structures identify entropy portions reduced precision.The ensuing depict negligible loss output when process saving higher proportion. Merits incorporating illustrated through statistics-inspired Sum Squared Error Normalized Cross Correlation error metric template matching Motion Estimation Disparity Estimation.The designs high appropriate perform better approximate use brute force quantization well reduce complexity.The this either lower using comparable cost minimal impact compared approaches.Efficacy employing signal shown proofs savings Field Programmable Gate Arrays implementations performance several real-world applications. 70% Squarer 50% reduction times Modified achieved approach.