FPGA Implementations of the AES Masked Against Power Analysis Attacks

摘要: Power analysis attacks are a serious treat for implementations of modern cryptographic algorithms. Masking is particularly appealing countermeasure against such since it increases the security to well quantifiable level and can be implemented without modifying underlying technology. Its main drawback performance overhead implies. For example, due prohibitive memory costs, straightforward application masking AES algorithm, with precomputed tables, hardly practical. In this paper, we exploit both increased size state-of-the-art reconfigurable hardware devices previous optimization techniques minimize occupation software S-boxes, in order provide an efficient FPGA implementation masked side-channel attacks. We describe two high throughput architectures, based on 32-bit 128-bit datapaths that suitable Xilinx Virtex-5 devices. way, demonstrate possibility efficiently combine technological advances algorithmic optimizations context.