作者: Kai Di Feng
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摘要: In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises first circuit located on an integrated circuit, where the includes voltage controlled oscillator for generating periodic output signal, phase detector controlling oscillator, charge pump modifying input to frequency divider in feedback path of multiplexer, and random number generator. The further second including multiplexer generator, wherein is programmable off coupled circuit. Additional systems structures are also presented.