Serial data communication interface architecture

摘要: A novel serial data communication interface architecture is provided having two modes of operation that are accessed through a chip select signal in combination with successive approximation registers (SARS). Once the internal conversion begins, may change to any state without interrupting process. Serial output and SARS lines tri-stated during conversion, while high. This allows input, output, serve other purposes conversion. If high at falling edge SARS, converted DO bits then an register. However, not immediately routed output. Clocking does resume until first transition low after SARS. The next initiated second back signaling end