A design-for-test technique for switched-capacitor filters
作者： M. Soma , V. Kolarik
DOI: 10.1109/VTEST.1994.292336
关键词:
摘要: The paper describes a design-for-test technique for switched-capacitor (SC) filters to improve controllability and observability of internal nodes. Timing strategies employing existing clock phases in SC circuits are used sensitize signal propagating paths, thus enhancing the circuit testability. overhead terms extra control logic is small (several simple gates). Since there no extraneous devices inserted analog path, performance penalty normal operation filters. >
ieeecomputersociety.org 参考文章(3)
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