A CMOS frequency synthesizer covering the lower and upper bands of 5GHz WLANs
作者： MN El-Gamal , A Marsolais , M Sawan , None
DOI: 10.1109/MWSCAS.2003.1562496
关键词:
摘要: This paper presents the design and experimental results of a 1.8V fractional-N frequency synthesizer. It is implemented in standard 0.18/spl mu/m digital CMOS process. A quadrature VCO, providing 4-phase output, uses combined current varactor tuning to enable 1.18GHz range. covers entire 5-6GHz span, making it suitable for wireless local area network (WLAN) applications, especially standards defined both lower (5.15-5.35GHz) upper (5.725-5.825GHz) unlicensed bands. The synthesizer phase noise band -107dBc/Hz @ 10MHz offset, -91dBc/Hz 10MHz. measured resolution 5.05MHz, settling time 520ps. All circuitry were optimized low power consumption. For example, prescaler/divider combination consumes 4.5mW compared 19mW reported [H. R. Rategh, H. Samavati T. Lee (2000)].
sci-hub.se 参考文章(19)
B. De Muer, M.S.J. Steyaert, A CMOS monolithic /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer for DCS-1800 IEEE Journal of Solid-state Circuits. ,vol. 37, pp. 835- 844 ,(2002) , 10.1109/JSSC.2002.1015680
R. Ahola, K. Stadius, K. Halonen, Design of a fully integrated 2 GHz CMOS frequency synthesizer international symposium on circuits and systems. ,vol. 2, pp. 160- 163 ,(1999) , 10.1109/ISCAS.1999.780643
Behzad Razavi, Monolithic phase-locked loops and clock recovery circuits : theory and design IEEE Press. ,(1996)
Koon Hung Lee, M.N. El-Gamal, A very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications international symposium on circuits and systems. ,vol. 1, pp. 125- 128 ,(2002) , 10.1109/ISCAS.2002.1009793
N. Krishnapura, P.R. Kinget, A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 1019- 1024 ,(2000) , 10.1109/4.848211
M.N. El-Gamal, K.H. Lee, T.K. Tsang, Very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications IEE Proceedings - Circuits, Devices and Systems. ,vol. 149, pp. 355- 362 ,(2002) , 10.1049/IP-CDS:20020605
H.R. Rategh, H. Samavati, T.H. Lee, A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 780- 787 ,(2000) , 10.1109/4.841507
Hong-ih Cong, Andrews, Boulin, San-Chin Fang, Hillenius, Michejda, A 2-ghz CMOS Dual-modulus Prescalar Ic international solid-state circuits conference. pp. 138- 139 ,(1988) , 10.1109/ISSCC.1988.663668
J.D. van der Tang, D. Kasperkovitz, A low-phase-noise reference oscillator with integrated pMOS varactors for digital satellite receivers IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 1238- 1243 ,(2000) , 10.1109/4.859517
Chih-Ming Hung, K.K. O, A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop IEEE Journal of Solid-state Circuits. ,vol. 37, pp. 521- 525 ,(2002) , 10.1109/4.991390