DMA controller with semaphore communication protocol

作者: Daniel C. Robbins

DOI:

关键词:

摘要: A device driver initiates a DMA transfer and repeatedly reads semaphore from specified location in system memory. Upon completion of transfer, controller writes containing status information to the memory, informing that is completed. cache memory for provided further reduce latency between transfers.

参考文章(34)
Kadangode K. Ramakrishnan, Douglas M. Washabaugh, Phillip J. Weeks, David Sawyer, Scheduling mechanism for network adapter to minimize latency and guarantee background processing time ,(1992)
Tsuyoshi Katayose, Yuko Mitsuhira, Data transfer control device using direct memory access ,(1992)
Dean A. Kalman, Robert D. Yoder, Serafin J. E. Garcia, Douglas R. Chisholm, Russell S. Padgett, Bus master interface circuit with transparent preemption of a data transfer operation ,(1990)