A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter
作者： Yanxiang Huang , Chunshu Li , Khaled Khalaf , Andre Bourdoux , Julien Verschueren
DOI: 10.1109/ASSCC.2016.7844203
关键词:
摘要: A complete Digital Front-End (DFE) processor for 60 GHz polar transmitter is presented. It avoids supply modulating, RF limiters, and AM detection circuits, compared to traditional analog-centric architectures. The front-end consists of i) a poly-phase Cascaded Integrator-Comb (CIC) filter spectrum shaping; ii) parallel COordinate Rotation DIgital Computer (CORDICs) rectangular-to-polar conversion; iii) Power Amplifier (PA) non-linearities pre-distortion units using Look-Up Tables (LUTs). designed in two-phase latch-based pipeline achieve throughput 4×1.76 Gsps. Implemented standard 28 nm CMOS technology, the DFE occupies 0.031 mm2 consumes 39mW from 0.9V supply. This result outperforms previously reported
sci-hub.se 参考文章(8)
Chunshu Li, Andre Bourdoux, Marian Verhelst, Yanxiang Huang, Min Li, Liesbet Van Der Perre, Sofie Pollin, <30 mW rectangular-to-polar conversion processor in 802.11ad polar transmitter international conference on acoustics, speech, and signal processing. pp. 1022- 1026 ,(2015) , 10.1109/ICASSP.2015.7178124
Jaimin Mehta, R. B. Staszewski, Oren Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari, Gennady Feygin, Sudheer Vemulapalli, Vasile Zoicas, Chih-Ming Hung, Nathen Barton, Imran Bashir, Kenneth Maggio, Michel Frechette, Meng-Chang Lee, John Wallberg, Patrick Cruise, Naveen Yanduru, A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC international solid-state circuits conference. pp. 58- 59 ,(2010) , 10.1109/ISSCC.2010.5434050
Jonathan Muller, Bruno Stefanelli, Antoine Frappe, Lu Ye, Andreia Cathelin, Ali Niknejad, Andreas Kaiser, A 7-Bit 18th Order 9.6 GS/s FIR Up-Sampling Filter for High Data Rate 60-GHz Wireless Transmitters IEEE Journal of Solid-state Circuits. ,vol. 47, pp. 1743- 1756 ,(2012) , 10.1109/JSSC.2012.2191677
D.D. Hwang, Dengwei Fu, A.N. Willson, A 400-MHz processor for the conversion of rectangular to polar coordinates in 0.25-/spl mu/m CMOS IEEE Journal of Solid-state Circuits. ,vol. 38, pp. 1771- 1775 ,(2003) , 10.1109/JSSC.2003.817588
Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez, A 13bits 4.096GHz 45nm CMOS digital decimation filter chain with Carry-Save format numbers Microprocessors and Microsystems. ,vol. 39, pp. 869- 878 ,(2015) , 10.1016/J.MICPRO.2014.11.003
Antonio Giuseppe Maria Strollo, Davide De Caro, Nicola Petra, None, A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 $\mu\hbox{m}$ CMOS IEEE Journal of Solid-state Circuits. ,vol. 43, pp. 2503- 2513 ,(2008) , 10.1109/JSSC.2008.2005816
Paul T. M. van Zeijl, Manel Collados, A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS compound semiconductor integrated circuit symposium. ,vol. 42, pp. 2204- 2211 ,(2007) , 10.1109/JSSC.2007.905239
Khaled Khalaf, Vojkan Vidojkovic, Kristof Vaesen, Michael Libois, Giovanni Mangraviti, Viki Szortyka, Chunshu Li, Bob Verbruggen, Mark Ingels, Andre Bourdoux, Charlotte Soens, Wim Van Thillo, John R. Long, Piet Wambacq, Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication IEEE Journal of Solid-state Circuits. ,vol. 51, pp. 1579- 1592 ,(2016) , 10.1109/JSSC.2016.2544784