Interface engineering of Si1−xGex gate stacks for high performance dual channel CMOS

摘要: In this paper, we discuss a technique for selective GeO x -scavenging which creates -free interfacial layer (IL) on Si 1−x Ge substrates. This process reduces interface trap density (N it ) and increases high-field hole mobility in pFETs. addition, identify the existence of electronic defect levels close to band edges associated with surface concentration at /IL interface. These defects act as carrier scattering centers severely degrading channel modulate device threshold voltage. By successfully eliminating component IL states interface, high over wide range inversion compressively-strained pFETs is demonstrated.