Processor, method, and data processing system employing a variable store gather window
作者： Robert H. Bell , Jeffrey Adam Stuecheli , Hugh Shen , Derek Edward Williams
DOI:
关键词:
摘要: A processor includes at least one instruction execution unit that executes store instructions to obtain operations and a queue coupled the unit. The entry in which gathers multiple during gathering window data portion of write transaction directed lower level memory. In addition, dispatch logic varies size optimize performance for different behaviors workloads.
lens.org 参考文章(8)
Rupaka Mahalingaiah, Thomas S. Green, Workload balancing in a microprocessor for reduced instruction dispatch stalling ,(1997)
Farnaz Mounes-Toussi, Donald Lee Freerksen, Circuit arrangement and method with state-based transaction scheduling ,(1999)
Nicholas J. Richardson, Bus interface unit having dual purpose transaction buffer ,(1998)
Terry J. Parks, Darius D. Gaskins, Store queue including a byte order tracking mechanism for maintaining data coherency ,(1994)
Rajesh Bhikhubhai Patel, Processor and method for store gathering through merged store operations ,(1996)
Paul Serris, Alexander Klaiber, David Dunn, Guillermo Rozas, Lacky Shah, Method and system for conservatively managing store capacity available to a processor issuing stores ,(2003)
Kazunori Miyamoto, Yasuhiko Saito, Control circuits comparing index offset and way for cache system and method of controlling cache system ,(2002)