Cache swizzle with inline transposition

摘要: A method and circuit arrangement selectively swizzle data in one or more levels of cache memory coupled to a processing unit based upon swizzle-related page attributes stored address translation structure such as an Effective To Real Translation (ERAT) Lookaside Buffer (TLB). may be accessed, for example, connection with access request page, that associated the used control whether is swizzled, if so, how formatted association handling request.