作者: Kuo-Sheng Chao
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摘要: A multi-bus I 2 C (inter integrated circuit) system includes an 1 controller ( 100 ), a CPU 200 bus 300 decoder circuit 400 and eight buses 510 - 580 ). The ) of the binary 410 latch buffer 420 NOT gates 431 438 NAND 441 448 is 3-to-8 decoder. can include any number according to particular requirements. In such cases, has required input ports output ports. For example, be 4-to-16