Phase-shift resistant frequency variable clock-pulse generator for semiconductor devices, has external clock output circuit for generating an external clock-signal from the divided clock-signal

摘要: Reduction in the clock-pulse frequency at which semiconductor devices are clocked results savings power of these but requires a clock- pulse generator designed with divider (11) for outputting divided clock-signal by dividing an input signal concordance ratio control signal. An external clock output circuit (13) generates from clock-signal, and internal (15) phase is adjusted to that phase-setting (15,18). A control-signal blocking-circuit (33) deactivates while clocking operative, so as generate given deactivated changing