Data processing apparatus for receiving and decoding words in which data is encoded by phase reversals or non-phase reversals of a signal of a predetermined frequency

摘要: A data processing apparatus for receiving and coded words each word including, in succession, a reference bit, start or command bits, flag stop bit parity bit. The various bits are encoded within corresponding number of periods by eighteen cycles 900 hertz signal. is reversed phase with respect to the represent logic "0" additional either not preceding thereby "1", respectively. accordance invention includes microprocessor which performs multiple sampling frequency comparison operations on detect lock onto then positions its internal timing so as take samples at midpoints successive perform reversals lack determine values other bits. performed tolerates slight shifts skewing data.