Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads

摘要: A processing unit for a data system includes cache memory having reservation logic and processor core coupled to the memory. The an execution that executes instructions in plurality of concurrent hardware threads including at least first second threads. include, within thread, load-reserve instruction identifies target address which is requested. additionally load records that, responsive detecting, identifying recorded by unit, blocks from establishing logic.