Inter thread trace alignment method and system for a multi-threaded processor

作者: Xufeng Chen , William C. Anderson , Louis Achille Giannini

DOI:

关键词:

摘要: Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in communications (e.g., CDMA) system. Inter-thread trace alignment with execution includes recording timing data relating to common predetermined event. Such an event may be number cycles since last thread initiated tracing or all threads terminated tracing. The at which initiates is referenced maintaining then updated associate time result permit aligning associated threads. Interrelated records reconstructing interdependent information operating multi-threaded as well synchronizing

参考文章(172)
Herbert S. Steelman, Paul H. Benson, Dwayne T. Crump, Steven T. Pancoast, Standby checkpoint to prevent data loss ,(1994)
Neal Margulis, I860 Microprocessor Architecture ,(1990)
Lucian Codrescu, Erich Plondke, William Anderson, Sujat Jamil, Muhammad Ahmed, Variable interleaved multithreaded processor method and system ,(2005)
Jason T. Nearing, Paul B. Rawlins, Zheng Xu, Suraj Bhaskaran, Techniques for tracing processes in a multi-threaded processor ,(2007)
Masaki c, o Fujitsu Limited Kiyota, Naohiro c, o Fujitsu Limited Ukai, Toshio c, o Fujitsu Limited Yoshida, Multithread processor and thread switching control method ,(2004)