Combined interleaver and deinterleaver, and turbo decoder comprising a combined interleaver and deinterleaver
作者： Jens Berkmann , Thomas Herndl
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摘要: A combined interleaving and deinterleaving circuit (IDL1) comprises a first data memory (RAM) for temporarily storing the to be interleaved or deinterleaved. address generator generates sequence of consecutive addresses second (AG) that represents instruction (α(i)). During mode involving reading process during writing process, logical means (XOR, MUX) causes addressed by (AG).
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