作者: Wlodek Kurjanowicz
DOI:
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摘要: An AND-type anti-fuse memory cell, and a array consisting of cells. Chains AND type cells are connected in series with each other, bitline contact, order to minimize the area occupied by array. Each cell includes an access transistor serially connectable or transistors other cells, device. The channel region is device, both regions covered same wordline. wordline driven programming voltage level for read reading