Pipelined cordic architectures for fast VLSI filtering and array processing

摘要: The paper presents a revised functional description of Volder's Coordinate Rotation Digital Computer algorithm (CORDIC), as well allied VLSI implementable processor architectures. Both pipelined and sequential structures are considered. In the general purpose or multi-function case, pipeline length (number cycles), function evaluation time accuracy all independent various executable functions. High regularity minimality data-paths, simplicity control circuits enhancement speed ensured, partly by mapping unified set micro-operations, invoking natural encoding angle parameters. approach benefits execution in array configurations, since it will allow pipelining at bit level, thereby providing fast implementations certain algorithms exhibiting substantial structural parallelism.