Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters

摘要: A methodology for generating structural descriptions of complex digital devices from high-level and specifications. The uses a systematic technique to map enforce consistency the semantics imbedded in intent original, descriptions. design activity is essentially series transformations operating upon various levels representations. At each level, intended meaning (semantics) formal software manipulations are captured derive more detailed level describing hardware meeting goals. Important features are: capturing users concepts, intent, specification, descriptions, constraints trade-offs; architectural partitioning; what-if analysis at high level; sizing estimation; timing trade-off; conceptual with implementation closure. includes using estimators, based on data gathered over number realized designs, partitioning evaluating prior logic synthesis. From description, physical device readily realized. Techniques provided estimating performance, behavioral/functional Given behavioral or block diagram description flow design, pin-to-pin minimum clock cycle can be estimated accurately. An RTL may thus synthesized such that imposed achieved. estimated, re-synthesized until arrived meets higher level.